Various layouts for cell circuits have been developed for semiconductor devices with linear-shaped diffusion fins, i.e. FinFET devices. An exemplary cell layout incorporating FinFETs is shown in FIG. 1. In this figure, the cell layout 101 includes diffusion regions 103 from which a number of linear, parallel fins 105 protrude from the substrate and extend in the direction of the cell width. The diffusion regions 103 and fins 105 together form the active regions 107. The cell layout 101 also includes a number of linear gate electrodes 109 that extend along the direction of the cell height in a perpendicular direction to the fins 105, and which wrap over the fins 105 and are electrically isolated from the fins by a gate oxide material (not shown). Various contacts are oriented perpendicular to the fins 105 but parallel to the gate electrodes 109, for example interconnect structures 111 for a source voltage 113 and 115, which are part of the metal 1 (M1) layer. In addition, the gate electrodes 109 cross-couple transistors formed from the upper and lower diffusion regions 103 through interconnect structures 119 for the drain voltage, which are connected through vias 117 to M1 layer segment 121. Two or more dummy gates 123 are formed at the edges of the cell.
As shown in FIG. 2A, two or more standard cells can be abutted into a single cell layout 201A in order to reduce the area of the layout and increase the number of transistors for a FinFET device. The cell layout 201A includes diffusion regions 103, fins 105, active regions 107, gate electrodes 109, interconnect structures 111 for the source voltage, source voltage 113 and 115 (which are part of the M1 layer), vias 117, interconnect structures 119 for the drain voltage, M1 layer segment 121, and three dummy gates 123. The diffusion regions 103 from the two cells meet in the middle of a dummy gate 123. However, the different height or number of fins 105 between the two abutted cells provides a non-uniform active region 107, resulting in a jog pattern in the active regions.
If the two diffusion regions are at different potentials, the jog pattern can be problematic due to leakage issues resulting in a discontinuous potential across the active regions. To solve the leakage problem, cell layout 201A has an active region cut 203 that separates the two cells over the dummy gate 123 where the two cells meet. The active region cut 203 causes a single diffusion break (SDB) 205. However, the contact region between the fins with the gate electrode is then reduced since the active region is rounded after lithography.
Alternatively, two cells may be abutted with a double diffusion break (DDB) to avoid the jog in the active regions, as illustrated in FIG. 2B. The cell layout 201B includes diffusion regions 103, fins 105, active regions 107, gate electrodes 109, interconnect structures 111 for the source voltage 113 and 115 (which are part of the M1 layer), vias 117, interconnect structures 119 for the drain voltage, M1 layer segment 121, and dummy gates 123. However, the cell layout 201B includes two dummy gates 123 with a DDB 207 therebetween where one cell abuts the other, and each diffusion region 103 goes to the edge of a dummy gate 123, thereby increasing the contact area. Although the DDB 207 avoids the leakage issues and the reduction in contact area after photolithography, the area is increased.
A need therefore exists for methodology enabling the production of layouts with continuous non-uniform active regions for FinFET standard cells and the resulting devices.